A lateral double-diffused MOS (LDMOS) transistor based on planar diffusion technology is generally used as a high-voltage MOS transistor. Owing to the higher input impedance in comparison to a bipolar transistor, an LDMOS transistor can realize a high power gain and/or a simpler gate driving circuit. Since an LDMOS transistor is a unipolar device, it advantageously exhibits little or no time delay when being turned off. The time delay usually originates from accumulated hydrophobic carriers.
FIG. 1 is a cross-sectional view illustrative of a conventional LDMOS transistor. The drawing illustrates two LDMOS transistors having an N channel arrayed over a substrate in a right and left symmetrical structure with a bulk pick-up region at the center.
Referring to FIG. 1, the conventional LDMOS transistor includes an N-type deep well 12 formed over a P-type substrate 11 to have a uniform impurity doping concentration throughout the entire region, an N-type well 14 and a P-type well 16 disposed in the N-type deep well 12 with a predetermined distance from each other, an N-type source region 17 and a P-type bulk pick-up region 18 formed in the P-type well 16, an N-type drain region 15 formed in the N-type well 14, a gate electrode 20 formed between the source region 17 and the drain region 15, and an insulation layer 21 interposed between the gate electrode 20 and the substrate 11. The insulation layer 21 includes a gate insulation layer 19 and a field oxide layer 13.
Design consideration for a high-voltage MOS transistor includes the minimizing of the specific on resistance (RSP) while maintaining a high breakdown voltage (BV) may be desirable.
In order to improve the breakdown voltage in the LDMOS transistor having the above-described structure, the impurity doping concentration should be reduced in the N-type deep well 12 or in a drift region (D). The area where the gate electrode 20 and the P-type well 16 overlap functions as a channel region C whereas the area from the end of the channel region C to the N-type drain region 15 is the drift region D.
When the impurity doping concentration is decreased in the N-type deep well 12 or in the drift region D in order to secure a sufficiently high breakdown voltage, the specific on resistance increases to thereby adversely affecting the operational current characteristic of the LDMOS transistor. Conversely, when the impurity doping concentration is increased in the N-type deep well 12 or in the drift region D in order to secure suitable operational current characteristic, the breakdown voltage characteristic may be adversely impacted. In other words, the breakdown voltage characteristic and the operational current characteristic may be considered as traded offs with respect to the impurity doping concentration of the N-type deep well 12 or the drift region D. It is thus desirable to secure both breakdown voltage characteristic and operational current characteristic that are suitable for a high-voltage MOS transistor.